{ "display_name" : "CPU Bottlenecks", "initial_mode_name" : "bottlenecks", "modes" : [ { "display_name" : "CPU Bottlenecks", "displays" : [ { "denominator" : 1, "elements" : [ { "color" : "green", "metric" : "useful" }, { "color" : "blue", "metric" : "processing" }, { "color" : "yellow", "metric" : "delivery" }, { "color" : "red", "metric" : "discarded" } ], "kind" : "normalized-area" } ], "documentation" : "The CPU Bottlenecks mode categorizes the sustainable instruction bandwidth of the CPU into four categories: one that represents useful work and three that represent various high-level sources of inefficiency.\n\nThe CPU pipeline is divided into two primary phases: _Instruction Delivery_ (obtaining instructions from memory along a predicted execution path) and _Instruction Processing_ (performing the action of the instructions). Both phases are potential sources of inefficiency, as well as the CPU-wide impact of mispredicting the execution path.\n\nMore specifically, bandwidth is analyzed at a micro-operation (µop) granularity, where instructions are typically translated into one µop, but some instructions require more than one.", "metrics" : [ { "aggregation" : "time-weighted-average", "display_name" : "Useful", "documentation" : "The fraction of sustainable instruction bandwidth that retired, meaning it was on the correct path through the code, and therefore contributed to forward progress of the application.\n\nMore specifically, this fraction directly relates to µops per cycle (µPC) and largely to instructions per cycle (IPC). Rather than presenting the measured µPC directly, this category shows the measured µPC divided by the maximum µPC for the particular core in order to provide a fraction of achievable µPC. A high fraction indicates that the code is executing in the CPU at a high rate.\n\nTo improve performance, improve the efficiency of the algorithm or the instruction sequences you use to implement the algorithm.", "name" : "useful", "synopsis" : "Fraction of sustainable instruction bandwidth that performed useful work." }, { "aggregation" : "time-weighted-average", "display_name" : "Discarded Bottleneck", "documentation" : "The fraction of sustainable instruction bandwidth wasted due to the effects of a branch misprediction or a pipeline restart.\n\nMore specifically, this fraction represents µop bandwidth wasted while processing down the wrong predicted path, as well as lost bandwidth required to recover from the misprediction. A high fraction indicates that the control flow or memory dependencies or both are difficult to predict and the CPU is throwing away a significant amount of predicted work.\n\nBecause the instruction window and overall speculative execution capability of the CPU tends to increase from family to family, the amount of discarded work due to similar misprediction rates may also increase.\n\nTo improve performance, focus on removing branches through conditional moves or altering data structures and decision trees for a more stable path through the code.", "name" : "discarded", "short_display_name" : "Discarded", "synopsis" : "Fraction of sustainable instruction bandwidth lost to incorrect speculative execution." }, { "aggregation" : "time-weighted-average", "display_name" : "Instruction Processing Bottleneck", "documentation" : "The fraction of instruction bandwidth lost because the Instruction Processing component is executing instructions at a rate lower than the sustainable bandwidth.\n\nMore specifically, this component maintains a forward-looking set of µops, called the instruction window, that the CPU collects from along a predicted instruction path and executes those µops as they become ready. This fraction represents µop bandwidth lost when the instruction window becomes full due to slow processing. A high fraction indicates insufficient instruction-level parallelism in the code, and that the Instruction Delivery component is inserting instructions into the instruction window faster than they are completed.\n\nTo improve performance, reduce memory delays and improve available instruction-level parallelism. For example, make data structure locality improvements, prefetch data from other cache lines, and unroll loops to create additional parallel computational sequences.", "name" : "processing", "short_display_name" : "Processing", "synopsis" : "Fraction of sustainable instruction bandwidth lost due to slow execution of instructions." }, { "aggregation" : "time-weighted-average", "display_name" : "Instruction Delivery Bottleneck", "documentation" : "The fraction of instruction bandwidth lost because the Instruction Delivery component did not deliver instructions at an adequate rate for the Instruction Processing component.\n\nMore specifically, the Instruction Delivery component reads bytes from memory, decodes them into instructions, and delivers them as µops into the Instruction Processing component's instruction window. This fraction represents lost bandwidth when the processing component has room in the instruction window, but new µops are not available from the predicted instruction stream. A high fraction indicates a higher Instruction Processing bandwidth might be possible if the Instruction Delivery component delivers new instructions faster.\n\nTo improve performance, reduce instruction memory delays by improving the locality of hot functions, and inline, unroll, and straighten common code sequences to create longer streams of sequentially fetched instructions. For less common code, optimize for smaller code size to improve cache performance using `-Os` with C-based languages or `-Osize` for Swift.", "name" : "delivery", "short_display_name" : "Delivery", "synopsis" : "Fraction of sustained bandwidth lost because insufficient instructions were provided for processing." }, { "aggregation" : "sum", "display_name" : "Cycles", "name" : "cycle", "synopsis" : "Cycles elapsed while the CPU was active." } ], "name" : "bottlenecks", "synopsis" : "Analyzes the efficiency of the sustainable CPU instruction bandwidth.", "thresholds" : [ { "display_name" : "High Discarded", "documentation" : "Remove branches through conditional moves or redesign data structures and decision trees for a more stable path through the code.", "expression" : "discarded", "next_modes" : [ "discarded_sampling" ], "synopsis" : "Incorrect speculative execution is wasting bandwidth.", "thresholds" : [ 0.1 ] }, { "display_name" : "High Processing Bottleneck", "documentation" : "Reduce memory delays and improve available instruction-level parallelism. For example, make data structure locality improvements, prefetch data from other cache lines, and unroll loops to create additional parallel computational sequences.", "expression" : "processing", "next_modes" : [ "processing", "l1d_miss_sampling" ], "synopsis" : "Serial data dependences with possibly long memory latencies are limiting bandwidth.", "thresholds" : [ 0.4 ] }, { "display_name" : "High Delivery Bottleneck", "documentation" : "Reduce memory delays by improving the locality of hot functions, and inline, unroll, and straighten code sequences to create longer streams of sequentially fetched instructions.", "expression" : "delivery", "next_modes" : [ "delivery" ], "synopsis" : "Slow instruction delivery is limiting bandwidth.", "thresholds" : [ 0.2 ] } ], "triggers" : [ ] }, { "display_name" : "Instruction Delivery Bottlenecks", "displays" : [ { "denominator" : 1, "elements" : [ { "color" : "yellow", "metric" : "delivery_latency" }, { "color" : "red", "metric" : "delivery_latency_icache" }, { "color" : "orange", "metric" : "delivery_latency_itlb" }, { "color" : "yellow", "metric" : "delivery_latency_other" }, { "color" : "purple", "metric" : "delivery_bandwidth" }, { "color" : "blue", "metric" : "delivery_bandwidth_taken_br" }, { "color" : "purple", "metric" : "delivery_bandwidth_other" } ], "kind" : "normalized-area" } ], "documentation" : "The Instruction Delivery Bottlenecks mode examines the efficiency of the Instruction Delivery component of the CPU, which reads instruction bytes from memory, translates them into instructions, and delivers them as µops into the Instruction Processing component.\n\nThis mode further categorizes the sustainable bandwidth lost due to delivery while the Instruction Processing component is able to accept additional µops, with some categories related to latency issues and others related to reduced bandwidth issues.\n\nUnlike the Instruction Processing Bottlenecks mode, which categorizes the overall activity of the Instruction Processing component each cycle, this analysis effectively _zooms in_ on the Instruction Delivery bottleneck to reveal further categorization.", "metrics" : [ { "aggregation" : "time-weighted-average", "display_name" : "Instruction Delivery Latency", "documentation" : "The fraction of sustainable bandwidth lost because the Instruction Delivery component experienced an event that delayed the delivery of the next instructions.\n\nTo improve performance, inline common code sequences and consolidate frequently executed functions together in memory. For less common code, optimize for smaller code size to improve cache performance using `-Os` with C-based languages or `-Osize` for Swift.", "name" : "delivery_latency", "short_display_name" : "Delivery Latency", "synopsis" : "Fraction of sustainable bandwidth lost because the Instruction Delivery component was unable to deliver any operations in a cycle." }, { "aggregation" : "time-weighted-average", "display_name" : "Instruction Delivery Latency from Instruction Cache", "documentation" : "The fraction of sustainable bandwidth lost because the Instruction Delivery component experienced an L1 Instruction Cache miss while reading instruction bytes from memory.\n\nA high fraction is often associated with fetching small blocks of infrequently used instructions scattered around memory.\n\nTo improve performance, inline common code sequences and consolidate frequently executed functions together in memory. For less common code, optimize for smaller code size to improve cache performance using `-Os` with C-based languages or `-Osize` for Swift.", "name" : "delivery_latency_icache", "short_display_name" : "L1IC Latency", "synopsis" : "Fraction of sustainable bandwidth lost due to an L1 Instruction Cache miss." }, { "aggregation" : "time-weighted-average", "display_name" : "Instruction Delivery Latency from Instruction TLB", "documentation" : "The fraction of sustainable bandwidth lost because the Instruction Delivery component experienced an L1 Instruction Translation Lookaside Buffer (TLB) miss while reading instruction bytes from memory.\n\nA high fraction is often associated with fetching instructions scattered across the memory space of the application.\n\nTo improve performance, consolidate frequently executed functions together in memory and inline common code sequences to create integrated streams of instructions. For less common code, optimize for smaller code size to improve cache performance using `-Os` with C-based languages or `-Osize` for Swift.", "name" : "delivery_latency_itlb", "short_display_name" : "L1ITLB Latency", "synopsis" : "Fraction of sustainable bandwidth lost due to an L1 Instruction Translation Lookaside Buffer (TLB) miss." }, { "aggregation" : "time-weighted-average", "display_name" : "Instruction Delivery Other Latency", "documentation" : "The fraction of sustainable bandwidth lost because the Instruction Delivery component experienced an event that delayed the delivery of the next instructions due to an undetermined cause.\n\nIn some cases, these delays might be artifacts of the other Instruction Delivery issues, and focusing on solutions for those issues can help with this category.", "name" : "delivery_latency_other", "short_display_name" : "Other Latency", "synopsis" : "Fraction of sustainable bandwidth lost due to an undetermined event that delayed the delivery of the next instructions." }, { "aggregation" : "time-weighted-average", "display_name" : "Instruction Delivery Bandwidth", "documentation" : "The fraction of the sustainable bandwidth lost because the Instruction Delivery component was unable to deliver µops at full bandwidth in a cycle.\n\nA high fraction is often associated with an instruction stream with too many taken branches, including calls and returns, leading to sequences that are shorter than the sustainable bandwidth per cycle.\n\nTo improve performance, inline, unroll, and straighten common code sequences to create longer streams of sequentially fetched instructions. For example, replace simple branches that skip assignments with conditional select or set instructions.", "name" : "delivery_bandwidth", "short_display_name" : "Delivery BW", "synopsis" : "Fraction of the sustainable bandwidth lost due to not delivering µops at full bandwidth." }, { "aggregation" : "time-weighted-average", "display_name" : "Instruction Delivery Bandwidth from Taken Branch", "documentation" : "The fraction of the sustainable bandwidth lost because the Instruction Delivery component was unable to deliver µops at full bandwidth in a cycle due to taken branches.\n\nA high fraction is often associated with an instruction stream with too many taken branches, including calls and returns, leading to sequences that are shorter than the sustainable bandwidth per cycle. These are often due to short loop bodies.\n\nTo improve performance, inline, unroll, and straighten common code sequences to create longer streams of sequentially fetched instructions. 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Consolidate frequently executed portions of functions together in memory. More consistent control flow can also help with prefetching instructions. For less common code, optimize for smaller code size to improve cache performance using `-Os` with C-based languages or `-Osize` for Swift.", "expression" : "delivery_latency", "next_modes" : [ ], "synopsis" : "Instruction Translation Lookaside Buffer (TLB) and Cache misses are causing delays.", "thresholds" : [ 0.25 ] }, { "display_name" : "High Instruction Delivery Latency from Instruction Cache", "documentation" : "Inline, unroll, and straighten common code sequences to create longer streams of sequentially fetched instructions. Consolidate frequently executed portions of functions together in memory. More consistent control flow can also help with prefetching instructions. For less common code, optimize for smaller code size to improve cache performance using `-Os` with C-based languages or `-Osize` for Swift.", "expression" : "delivery_latency_icache", "next_modes" : [ ], "synopsis" : "Instruction Cache misses are causing delays.", "thresholds" : [ 0.2 ] }, { "display_name" : "High Instruction Delivery Latency from Instruction TLB", "documentation" : "Consolidate frequently executed portions of functions together in memory. Inline common code sequences to create integrated streams of instructions. More consistent control flow can also help with prefetching instructions. For less common code, optimize for smaller code size to improve cache performance using `-Os` with C-based languages or `-Osize` for Swift.", "expression" : "delivery_latency_itlb", "next_modes" : [ ], "synopsis" : "Instruction Translation Lookaside Buffer (TLB) misses are causing delays.", "thresholds" : [ 0.05 ] }, { "display_name" : "High Instruction Delivery Other Latency", "documentation" : "In some cases, these delays might be artifacts of the other Instruction Delivery causes. Follow the recommendations for these other significant causes.", "expression" : "delivery_latency_other", "next_modes" : [ ], "synopsis" : "An undetermined event is causing delays.", "thresholds" : [ 0.15 ] }, { "display_name" : "Bottlenecked Instruction Delivery Bandwidth", "documentation" : "There are too few sequential instructions between taken branches. Inline, unroll, and straighten common code sequences to create longer streams of sequentially fetched instructions.", "expression" : "delivery_bandwidth", "next_modes" : [ ], "synopsis" : "Short sequential code sequences are limiting delivery.", "thresholds" : [ 0.15 ] }, { "display_name" : "Bottlenecked Instruction Delivery Bandwidth from Taken Branch", "documentation" : "There are too few sequential instructions between taken branches. Inline, unroll, and straighten common code sequences to create longer streams of sequentially fetched instructions.", "expression" : "delivery_bandwidth_taken_br", "next_modes" : [ ], "synopsis" : "Short sequential code sequences are limiting delivery.", "thresholds" : [ 0.1 ] }, { "display_name" : "High Instruction Delivery Other Bandwidth", "documentation" : "In some cases, these delays might be artifacts of the other Instruction Delivery causes. Follow the recommendations for these other significant causes.", "expression" : "delivery_bandwidth_other", "next_modes" : [ ], "synopsis" : "An undetermined event is causing delays.", "thresholds" : [ 0.1 ] } ], "triggers" : [ ] }, { "display_name" : "Instruction Processing Bottlenecks", "displays" : [ { "denominator" : 1, "elements" : [ { "color" : "blue", "metric" : "executing" }, { "color" : "purple", "metric" : "memory_miss_executing" }, { "color" : "red", "metric" : "memory_miss" }, { "color" : "orange", "metric" : "non_critical_memory_miss" }, { "color" : "green", "metric" : "mte_tag_check" }, { "color" : "yellow", "metric" : "execution_latency_without_sme" }, { "color" : "yellow", "metric" : "execution_latency" } ], "kind" : "normalized-area" }, { "color" : "blue", "kind" : "bar", "metric" : "sme_stream_enable" } ], "documentation" : "The Instruction Processing Bottlenecks mode examines the efficiency of the Instruction Processing component of the CPU.\n\nThis component maintains a forward-looking set of instructions (called the instruction window) that it collects along a predicted instruction path, and executes those instructions as they become ready. This mode categorizes overall activity of the Instruction Processing component each cycle, when there is at least 1 µop in the instruction window, into a number of categories.\n\nUnlike the Instruction Delivery Bottleneck mode which further categorizes the cause of each lost delivery, this mode examines all cycles where there is work to do in the instruction window.\n\nSpecifically, this mode helps to analyze whether the workload is more compute-bound (bottlenecked on compute instruction bandwidth and latency) or memory-bound (bottlenecked on obtaining data from the memory hierarchy). Because of the large instruction window, this is a complex question because the Instruction Processing component can often find some speculative work to do even while waiting for data to be supplied from a distant source, and can have requests outstanding for many (speculative) memory accesses at any time.", "metrics" : [ { "aggregation" : "time-weighted-average", "display_name" : "Critical L1D Cache Miss", "documentation" : "The fraction of cycles where the instruction window contains µops, did not execute any of them, and the oldest tracked load or store operation is experiencing an L1D Cache miss.\n\nCombined with the _Critical L1D Cache Miss While Executing_ category, the combined fraction represents the overall impact of a critical memory miss, and generally reflects the degree to which the workload is memory bound.\n\nA high fraction is often associated with scattered accesses to data memory such that there is poor cache-line reuse with access patterns that are difficult for the CPU to predict.\n\nTo improve performance, reduce the working set of data and access your data in regular, strided patterns. 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However, the Instruction Processing component is still able to find µops to execute.\n\nTo improve performance, reduce the working set of data and access your data in regular, strided patterns. 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These are typically the result of complex or irregular execution patterns.\n\nTo improve performance, focus on removing branches through conditional moves or altering data structures and decision trees for a more stable path through the code.", "metrics" : [ { "aggregation" : "sum", "display_name" : "Unpredicted Memory Dependencies", "documentation" : "Counts and identifies retired store instructions that caused a pipeline flush and replay of loads and subsequent instructions because of unpredicted memory dependency.\n\nTo improve performance, access your data in more regular patterns. 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